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Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].
Ch. Ashok Babu. 2013. \u201cAn Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue F14): .
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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Total Score: 103
Country: India
Subject: Global Journal of Research in Engineering - F: Electrical & Electronic
Authors: Ch. Ashok Babu, J.V.R. Ravindra, K. Lal Kishore (PhD/Dr. count: 0)
View Count (all-time): 228
Total Views (Real + Logic): 4620
Total Downloads (simulated): 2351
Publish Date: 2013 11, Sat
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Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].
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