An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology

α
Ch. Ashok Babu
Ch. Ashok Babu
σ
J.V.R. Ravindra
J.V.R. Ravindra
ρ
K. Lal Kishore
K. Lal Kishore
α Jawaharlal Nehru Technological University, Hyderabad

Send Message

To: Author

An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology

Article Fingerprint

ReserarchID

575BH

An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology Banner

AI TAKEAWAY

Connecting with the Eternal Ground
  • English
  • Afrikaans
  • Albanian
  • Amharic
  • Arabic
  • Armenian
  • Azerbaijani
  • Basque
  • Belarusian
  • Bengali
  • Bosnian
  • Bulgarian
  • Catalan
  • Cebuano
  • Chichewa
  • Chinese (Simplified)
  • Chinese (Traditional)
  • Corsican
  • Croatian
  • Czech
  • Danish
  • Dutch
  • Esperanto
  • Estonian
  • Filipino
  • Finnish
  • French
  • Frisian
  • Galician
  • Georgian
  • German
  • Greek
  • Gujarati
  • Haitian Creole
  • Hausa
  • Hawaiian
  • Hebrew
  • Hindi
  • Hmong
  • Hungarian
  • Icelandic
  • Igbo
  • Indonesian
  • Irish
  • Italian
  • Japanese
  • Javanese
  • Kannada
  • Kazakh
  • Khmer
  • Korean
  • Kurdish (Kurmanji)
  • Kyrgyz
  • Lao
  • Latin
  • Latvian
  • Lithuanian
  • Luxembourgish
  • Macedonian
  • Malagasy
  • Malay
  • Malayalam
  • Maltese
  • Maori
  • Marathi
  • Mongolian
  • Myanmar (Burmese)
  • Nepali
  • Norwegian
  • Pashto
  • Persian
  • Polish
  • Portuguese
  • Punjabi
  • Romanian
  • Russian
  • Samoan
  • Scots Gaelic
  • Serbian
  • Sesotho
  • Shona
  • Sindhi
  • Sinhala
  • Slovak
  • Slovenian
  • Somali
  • Spanish
  • Sundanese
  • Swahili
  • Swedish
  • Tajik
  • Tamil
  • Telugu
  • Thai
  • Turkish
  • Ukrainian
  • Urdu
  • Uzbek
  • Vietnamese
  • Welsh
  • Xhosa
  • Yiddish
  • Yoruba
  • Zulu

Abstract

Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].

References

15 Cites in Article
  1. Md Manish Kumar1,Anwar Hussain1,K Sajal,Paul2 (2013). An Improved SOI CMOS Technology Based Circuit Technique for Effective Reduction of Standby Subthreshold Leakage.
  2. Y Kado (1997). The Potential of Ultrathin-Film SOI Devices for Low-Power and High-Speed Applications.
  3. S Cristoloveanu,G Reichert (1998). Recent advances in SOI materials and device technologies for high temperature.
  4. R Reedy (1999). Single Chip Wireless Systems Using SOI.
  5. S Abou-Samra,A Guyot (1998). Performance/ Complexity Space Exploration: Bulk vs. SOI.
  6. N Zhuang,H Wu (1992). A New Design of the CMOS Full Adder.
  7. R Navi,Md,Reza Saatchi,O Daei (2009). Design and Analysis of Low Power High Speed Hybrid Alternative Full Adder Circuits.
  8. D Soudris,V Pavlidis,A Thanailakis (2001). Designing low-power energy recovery adders based on pass transistor logic.
  9. R Shalem,E John,L John (null). A novel low power energy recovery full adder cell.
  10. E Chew,M Phyu,W Goh (2009). Ultra Low-Power Full-Adder for Biomedical Applications.
  11. S Goel,A Kumar,M Bayoumi (2006). Design of robust, energy efficient full adders for deep-submicrometer design using hybrid CMOS logic style.
  12. Antonio Blotti,Maurizio Castellucci,Roberto Saletti (2002). Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library.
  13. K Dhireesha,John (2005). Implementation of Low Power Digital Multipliers Using 10 Transistor Adder Blocks.
  14. M Alioto,G Palumbo (2000). Performance Evaluation of Adiabatic Gates.
  15. A Blotti,S Pascoli,R Saletti (2002). A comparison of some circuit schemes for semi-reversible adiabatic logic.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Ch. Ashok Babu. 2013. \u201cAn Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue F14): .

Download Citation

Issue Cover
GJRE Volume 13 Issue F14
Pg. 27- 30
Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Version of record

v1.2

Issue date

November 30, 2013

Language
en
Experiance in AR

Explore published articles in an immersive Augmented Reality environment. Our platform converts research papers into interactive 3D books, allowing readers to view and interact with content using AR and VR compatible devices.

Read in 3D

Your published article is automatically converted into a realistic 3D book. Flip through pages and read research papers in a more engaging and interactive format.

Article Matrices
Total Views: 4620
Total Downloads: 2351
2026 Trends
Related Research

Published Article

Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].

Our website is actively being updated, and changes may occur frequently. Please clear your browser cache if needed. For feedback or error reporting, please email [email protected]

Request Access

Please fill out the form below to request access to this research paper. Your request will be reviewed by the editorial or author team.
X

Quote and Order Details

Contact Person

Invoice Address

Notes or Comments

This is the heading

Lorem ipsum dolor sit amet, consectetur adipiscing elit. Ut elit tellus, luctus nec ullamcorper mattis, pulvinar dapibus leo.

High-quality academic research articles on global topics and journals.

An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology

Ch. Ashok Babu
Ch. Ashok Babu Jawaharlal Nehru Technological University, Hyderabad
J.V.R. Ravindra
J.V.R. Ravindra
K. Lal Kishore
K. Lal Kishore

Research Journals