An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology

Ch. Ashok Babu; J.V.R. Ravindra; K. Lal Kishore

An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology

Ch. Ashok Babu * §

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J.V.R. Ravindra

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K. Lal Kishore

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§ Swami Vivekananda Institute of Technology

An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology

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Abstract

Power has become a burning issue in modern VLSI design, as the technology advances especially below 45nm technology, Leakage power become more problem apart of the dynamic power. This paper presents a full adder with novel PMOS and NMOS which consume less power compare to conventional full adder and DTMOS full adder, this paper shows different types of adders and their power consumption, area and delay. All the experiments have been carried out using cadence virtuoso design lay out editor which shows power consumption of different types of adders[1-2].

References

15 Cites in Article

Reference Format

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Ch. Babu, J.V.R. Ravindra, K. Kishore. 2013. "An Adder with Novel PMOS and NMOS for Ultra Low Power Applications in Deep Submicron Technology". Global Journal of Research in Engineering, Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 13 (GJRE Volume 13 Issue F14).

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GJRE Volume 13 Issue F14

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords

average power Delay DTMOS leakage power PDP

Classification

GJRE-F Classification FOR Code: 090607

Submission ReceivedDecember 10, 2012
Peer Review Double Blind
Handling Editor
Accepted January 1, 2013
Published January 15, 2013

Version of record

v1.2

Issue date

November 30, 2013

Language

English

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Article Matrices

Total Score: 103

Country: India

Subject: Global Journal of Research in Engineering

Authors: Ch. Ashok Babu, J.V.R. Ravindra, K. Lal Kishore (PhD/Dr. count: 0)

View Count (all-time): 345

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Publish Date: 2013 01, Tue

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Total Views: 1.6K

Total Downloads: 114

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