Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

Md. Masood Ahmad

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Dr. K.Manjunathachari

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Dr. K.Lalkishore

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GITAM University

Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

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Abstract

In this paper a new full adder is proposed. The number of Transistors used in the proposed full adder is 13.Average leakage is 62% of conventional 28 transistor CMOS full adder. The leakage power reduction results in overall power reduction. The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools.

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Md. Masood Ahmad. 2016. \u201cDesign and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology\u201d. Global Journal of Computer Science and Technology - A: Hardware & Computation GJCST-A Volume 16 (GJCST Volume 16 Issue A1): .

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GJCST Volume 16 Issue A1
Pg. 25- 31

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

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Classification

G.4, B.3.2

Submission ReceivedDecember 11, 2015
Peer Review Double Blind
Handling Editor
Accepted January 4, 2016
Published January 15, 2016

Version of record

v1.2

Issue date

September 13, 2016

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Article Matrices

Total Score: 113

Country: India

Subject: Global Journal of Computer Science and Technology - A: Hardware & Computation

Authors: Md. Masood Ahmad, Dr. K.Manjunathachari, Dr. K.Lalkishore (PhD/Dr. count: 2)

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