Design and Implementation of Low Power 12-Bit 100-MS/S Pipelined ADC Using Open-Loop Residue Amplification

Mr. Appa Rao M.
Mr. Appa Rao M. * §
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prrjntu
prrjntu
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Cyril Prasanna Raj P.
Cyril Prasanna Raj P.
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§ JNTU College of Engineering. Ananthapur.

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Design and Implementation of Low Power 12-Bit 100-MS/S Pipelined ADC Using Open-Loop Residue Amplification

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Background

Abstract

In this paper a high speed, low power 12-bit, analog-to-digital converter in CMOS 0.13 micron technology that makes it suitable for UWB is designed and implemented. For designing the particular ADC a bottom up hierarchical method is adopted. First according to the specification, the design of aspect ratio of the transistors used in our design is done. There were many challenges throughout the design process, including determining the matching requirements of the devices, investigating what percentage of segmentation to be used to design the whole system. For checking the functionality of the whole system a spice code is written using HSPICE by defining all blocks in the circuit as sub circuits. Then a schematic capture is done using schematic composer from virtuoso stating from bottom level to top level. Finally the layout for the complete ADC is done using Electric Layout editor. A 12-bit pipelined ADC that can operate at maximum frequency of 100 MSPS, and power consumption less than 70mW is designed and implemented.

References

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Mr. Appa Rao M., prrjntu, Cyril Prasanna Raj P.. 2012. "Design and Implementation of Low Power 12-Bit 100-MS/S Pipelined ADC Using Open-Loop Residue Amplification". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 12 (GJRE Volume 12 Issue F11).

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  • CC-BY-ND-NC 4.0
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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Keywords
ADCCMOShigh Accuracyhigh speedLow powerlow voltageMulti – Stage
Classification
GJRE-F Classification FOR Code: 090699
  • Submission ReceivedFebruary 9, 2012
  • Peer Review Double Blind
    Handling Editor
  • Accepted March 5, 2012
  • Published March 15, 2012
Version of record

v1.2

Issue date
October 25, 2012

Language
English
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Design and Implementation of Low Power 12-Bit 100-MS/S Pipelined ADC Using Open-Loop Residue Amplification

Mr. M.
Mr. M. JNTU College of Engineering. Ananthapur.
Cyril P.
Cyril P.
  • Submission ReceivedFebruary 9, 2012
  • Peer Review Double Blind
    Handling Editor
  • Accepted March 5, 2012
  • Published March 15, 2012