Design of a Novel Low-Power SRAM Column

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Sunil Ojha
Sunil Ojha
σ
Sunil Kumar Ojha
Sunil Kumar Ojha
α Amity University

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Design of a Novel Low-Power SRAM Column

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Abstract

A novel SRAM column was designed. SRAM column includes SRAM cell, column select circuit, precharging circuit, and sense amplifier. The transmission gates are used for word line access in place of pass transistors which rectify the voltage drop problem; also there is an NMOS switch at the bottom of the cell which restricts the short circuit current flowing through the cell during operation. Using the standard process parameters of the PTM 7nm transistor model the SRAM column was simulated by HSPICE. The simulation results indicate the proper logic operation of the column and also it shows the low power operation.

References

11 Cites in Article
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  2. S Nakata (2009). Adiabatic SRAM with a Large Margin of VT Variation by Controlling the Cell-Power-Line and Word-Line Voltage.
  3. Kevin Zhang (2008). Low-Power SRAMs in Nanoscale CMOS Technologies.
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  5. W Athes (1994). Low-power Digital systems based on adiabatic-switching principles.
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  11. Unknown Title.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Sunil Ojha. 2014. \u201cDesign of a Novel Low-Power SRAM Column\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F5): .

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Journal Specifications

Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

Version of record

v1.2

Issue date

August 4, 2014

Language
en
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A novel SRAM column was designed. SRAM column includes SRAM cell, column select circuit, precharging circuit, and sense amplifier. The transmission gates are used for word line access in place of pass transistors which rectify the voltage drop problem; also there is an NMOS switch at the bottom of the cell which restricts the short circuit current flowing through the cell during operation. Using the standard process parameters of the PTM 7nm transistor model the SRAM column was simulated by HSPICE. The simulation results indicate the proper logic operation of the column and also it shows the low power operation.

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Design of a Novel Low-Power SRAM Column

Sunil Kumar Ojha
Sunil Kumar Ojha

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