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A novel SRAM column was designed. SRAM column includes SRAM cell, column select circuit, precharging circuit, and sense amplifier. The transmission gates are used for word line access in place of pass transistors which rectify the voltage drop problem; also there is an NMOS switch at the bottom of the cell which restricts the short circuit current flowing through the cell during operation. Using the standard process parameters of the PTM 7nm transistor model the SRAM column was simulated by HSPICE. The simulation results indicate the proper logic operation of the column and also it shows the low power operation.
Sunil Ojha. 2014. "Design of a Novel Low-Power SRAM Column". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F5).
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
v1.2
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Total Score: 101
Country: India
Subject: Global Journal of Research in Engineering
Authors: Sunil Kumar Ojha (PhD/Dr. count: 0)
View Count (all-time): 350
Total Views (Real + Logic): 1462
Total Downloads (simulated): 102
Publish Date: 2014 01, Wed
Monthly Totals (Real + Logic):
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