Fast Implementation of Lifting Based DWT Architecture For Image Compression

Fast Implementation of Lifting Based DWT Architecture For Image Compression

Dr. M. Nagabushanam 1. B.E Electronics Engineering Bangalore University 1997 Second class,53.66% 2. M.Tech Electronics Engineering Visvesvaraya TechnologicalUniversity, Belguam 2003 First ,62.4% 3 Ph.D VLSI Anna University,Chennai 2017

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S. Ramachandran

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α Anna University, Coimbatore, India.

Fast Implementation of Lifting Based DWT Architecture For Image Compression

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Abstract

Technological growth in semiconductor industry have led to unprecedented demand for faster, area efficient and low power VLSI circuits for complex image processing applications. DWT-IDWT is one of the most popular IP that is used for image transformation. In this work, a high speed, low power DWT/IDWT architecture is designed and implemented on ASIC using 130nm Technology. 2D DWT architecture based on lifting scheme architecture uses multipliers and adders, thus consuming power. This paper addresses power reduction in multiplier by proposing a modified algorithm for BZFAD multiplier. The proposed BZFAD multiplier is 65% faster and occupies 44% less area compared with the generic multipliers. The DWT architecture designed based on modified BZFAD multiplier achieves 35% less power reduction and operates at frequency of 200MHz with latency of 1536 clock cycles for 512×512 image. The developed DWT can be used as an IP for VLSI implementation.

References

23 Cites in Article

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

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No ethics committee approval was required for this article type.

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Not applicable for this article.

How to Cite This Article

Dr. M. Nagabushanam. 2012. \u201cFast Implementation of Lifting Based DWT Architecture For Image Compression\u201d. Global Journal of Computer Science and Technology - F: Graphics & Vision GJCST-F Volume 12 (GJCST Volume 12 Issue F11): .

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GJCST Volume 12 Issue F11
Pg. 23- 29

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords

BZFAD multiplier DWT FPGA Image Compression Lifting Scheme

Submission ReceivedFebruary 6, 2012
Peer Review Double Blind
Handling Editor
Accepted March 1, 2012
Published March 15, 2012

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July 31, 2012

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Total Score: 107

Country: Unknown

Subject: Global Journal of Computer Science and Technology - F: Graphics & Vision

Authors: Dr. M. Nagabushanam, S. Ramachandran (PhD/Dr. count: 1)

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Total Downloads: 2462

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