Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

1
Rabiul Islam
Rabiul Islam
2
Dr. Sheikh Md. Rabiul Islam
Dr. Sheikh Md. Rabiul Islam
3
Md. Jobayer Hossain
Md. Jobayer Hossain
1 to 3 Khulna University of Engineering and Technology

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

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No ethics committee approval was required for this article type.

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Not applicable for this article.

Rabiul Islam. 2012. \u201cGate Level Design of a Digital Clock with Asynchronous-Synchronous Logic\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 12 (GJRE Volume 12 Issue F4): .

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Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

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April 3, 2012

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English

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Gate Level Design of a Digital Clock with Asynchronous-Synchronous Logic

Dr. Sheikh Md. Rabiul Islam
Dr. Sheikh Md. Rabiul Islam
Md. Jobayer Hossain
Md. Jobayer Hossain Khulna University of Engineering and Technology

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