Low Power Conditional Sum Adder using modified Ripple Carry Adder

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Anjana R.
Anjana R.
2
Vicky Kanoji
Vicky Kanoji
3
Ajay Somkumar
Ajay Somkumar

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GJRE Volume 14 Issue F5

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Carry select adder (CSeLA) is mainly used to alleviate the propagation delay caused by carry bit and upon which sum bit is generated. It produces n+1 sum from n bits. In this Paper, a simple Gate level implementation of regular Carry Select Adder is compared with our proposed work. Based on the comparison made in terms of power, delay and area, it is found that there is considerable reduction in area and power with delay overhead. Both regular and proposed methods are modeled using 180nm CMOS technology. From the results obtained, it is clear that proposed CSeLA is better than regular CSeLA.

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7 Cites in Articles

References

  1. O Bedrij (1962). Carry-Select Adder.
  2. B Ramkumar,H Kittur,P Kannan (2010). ASIC Implementation Of Modified Faster Carry Save Adder.
  3. T Ceiang,M Hsiao (1998). Carry-Select Adder Using Single Ripple Carry Adder.
  4. Y Kim,L.-S Kim (2001). 64-Bit Carry-Select Adder With Reduced Area.
  5. J Rabaey (2001). Digtal Integrated Circuits-A Design Perspective.
  6. Y He,C Chang,J Gu (2005). An Area Efficient 64-Bit Square Root Carry-Select Adder For Lowpower Applications.
  7. B Ramkumar,Harish Kittur (2012). Low-Power and Area-Efficient Carry Select Adder.

Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

Anjana R.. 2014. \u201cLow Power Conditional Sum Adder using modified Ripple Carry Adder\u201d. Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F5): .

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Crossref Journal DOI 10.17406/gjre

Print ISSN 0975-5861

e-ISSN 2249-4596

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v1.2

Issue date

August 4, 2014

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English

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Carry select adder (CSeLA) is mainly used to alleviate the propagation delay caused by carry bit and upon which sum bit is generated. It produces n+1 sum from n bits. In this Paper, a simple Gate level implementation of regular Carry Select Adder is compared with our proposed work. Based on the comparison made in terms of power, delay and area, it is found that there is considerable reduction in area and power with delay overhead. Both regular and proposed methods are modeled using 180nm CMOS technology. From the results obtained, it is clear that proposed CSeLA is better than regular CSeLA.

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Low Power Conditional Sum Adder using modified Ripple Carry Adder

Anjana R.
Anjana R.
Vicky Kanoji
Vicky Kanoji
Ajay Somkumar
Ajay Somkumar

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