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Carry select adder (CSeLA) is mainly used to alleviate the propagation delay caused by carry bit and upon which sum bit is generated. It produces n+1 sum from n bits. In this Paper, a simple Gate level implementation of regular Carry Select Adder is compared with our proposed work. Based on the comparison made in terms of power, delay and area, it is found that there is considerable reduction in area and power with delay overhead. Both regular and proposed methods are modeled using 180nm CMOS technology. From the results obtained, it is clear that proposed CSeLA is better than regular CSeLA.
Anjana R., Vicky Kanoji, asomkumar. 2014. "Low Power Conditional Sum Adder using modified Ripple Carry Adder". Global Journal of Research in Engineering - F: Electrical & Electronic GJRE-F Volume 14 (GJRE Volume 14 Issue F5).
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
v1.2
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Total Score: 103
Country: India
Subject: Global Journal of Research in Engineering
Authors: Anjana R., Vicky Kanoji, Ajay Somkumar (PhD/Dr. count: 0)
View Count (all-time): 369
Total Views (Real + Logic): 2005
Total Downloads (simulated): 136
Publish Date: 2014 01, Wed
Monthly Totals (Real + Logic):
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