Performance Analysis of Modified Lifting Based DWT Architecture and FPGA Implementation for Speed and Power

Article ID

CSTGV85NTO

Performance Analysis of Modified Lifting Based DWT Architecture and FPGA Implementation for Speed and Power

Prof.C. Chandra Sekhar
Prof.C. Chandra Sekhar
Dr. S.Narayana Reddy
Dr. S.Narayana Reddy
DOI

Abstract

Demand for high speed and low power architecture for DWT computation have led to design of novel algorithms and architecture. In this paper we design, model and implement a hardware efficient, high speed and power efficient DWT architecture based on modified lifting scheme algorithm. The design is interfaced with SIPO and PISO to reduce the number of I/O lines on the FPGA. The design is implemented on Spartan III device and is compared with lifting scheme logic. The proposed design operates at frequency of 280 MHz and consumes power less than 42 mW. The presynthesis and post-synthesis results are verified and suitable test vectors are used in verifying the functionality of the design. The design is suitable for real time data processing.

Performance Analysis of Modified Lifting Based DWT Architecture and FPGA Implementation for Speed and Power

Demand for high speed and low power architecture for DWT computation have led to design of novel algorithms and architecture. In this paper we design, model and implement a hardware efficient, high speed and power efficient DWT architecture based on modified lifting scheme algorithm. The design is interfaced with SIPO and PISO to reduce the number of I/O lines on the FPGA. The design is implemented on Spartan III device and is compared with lifting scheme logic. The proposed design operates at frequency of 280 MHz and consumes power less than 42 mW. The presynthesis and post-synthesis results are verified and suitable test vectors are used in verifying the functionality of the design. The design is suitable for real time data processing.

Prof.C. Chandra Sekhar
Prof.C. Chandra Sekhar
Dr. S.Narayana Reddy
Dr. S.Narayana Reddy

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Dr. C.Chandrasekhar. 2012. “. Global Journal of Computer Science and Technology – F: Graphics & Vision GJCST-F Volume 12 (GJCST Volume 12 Issue F12): .

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Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

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GJCST Volume 12 Issue F12
Pg. 41- 50
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Performance Analysis of Modified Lifting Based DWT Architecture and FPGA Implementation for Speed and Power

Prof.C. Chandra Sekhar
Prof.C. Chandra Sekhar
Dr. S.Narayana Reddy
Dr. S.Narayana Reddy

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