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ReserarchID
SQR91
Crossref Journal DOI 10.17406/gjcst
Print ISSN 0975-4350
e-ISSN 0975-4172
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This paper attempted to assess the attitudes of students in
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This article discusses the architecture design of DMA controller on high performance GPS receiver based on RTEMS. We achieve the optimal integration of DMA IP and navigation baseband system. We designed the hardware architecture of DMA IP and make full use of hardware performance with the idea of multiplexing. We use register and FIFO buffer to achieve read-write control. And we design the DMA controller with Verilog HDL. Finally we verify the design on Altera Cyclone4 FPGA. The result demonstrates that DMA controller can ease the CPU’s burden and shorten the acquisition & tracking time thus improving the performance of the whole system.
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