The Implementation of DMA Controller on Navigation Baseband SoC

§ Guangdong University of Technology

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The Implementation of DMA Controller on Navigation Baseband SoC

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Abstract

This article discusses the architecture design of DMA controller on high performance GPS receiver based on RTEMS. We achieve the optimal integration of DMA IP and navigation baseband system. We designed the hardware architecture of DMA IP and make full use of hardware performance with the idea of multiplexing. We use register and FIFO buffer to achieve read-write control. And we design the DMA controller with Verilog HDL. Finally we verify the design on Altera Cyclone4 FPGA. The result demonstrates that DMA controller can ease the CPU’s burden and shorten the acquisition & tracking time thus improving the performance of the whole system.

References

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Funding

No external funding was declared for this work.

Conflict of Interest

The authors declare no conflict of interest.

Ethical Approval

No ethics committee approval was required for this article type.

Data Availability

Not applicable for this article.

How to Cite This Article

Abdulraqeb Alnabihi. 2015. "The Implementation of DMA Controller on Navigation Baseband SoC". Global Journal of Computer Science and Technology - A: Hardware & Computation GJCST-A Volume 15 (GJCST Volume 15 Issue A2).

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Journal Specifications

Crossref Journal DOI 10.17406/gjcst

Print ISSN 0975-4350

e-ISSN 0975-4172

Keywords
Classification
GJCST-A Classification B.3.2
B.5.1
Version of record

v1.2

Issue date
November 9, 2015

Language
English
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The Implementation of DMA Controller on Navigation Baseband SoC

Abdulraqeb Alnabihi
Abdulraqeb Alnabihi Guangdong University of Technology