Vasanth Kumar TR
Wireless FPGA Semiconductor Fixed wireless Physical layer Wireless transmission Electrical and Electronic Engineering

Bio

Vasanth Kumar TR is a researcher affiliated with Jain University in Bengaluru, Karnataka, India. His work focuses on FPGA-based implementations, particularly in the domain of wireless communications and OFDM systems. He has authored a paper titled 'FPGA Physical Layer Implementation of Fixed WIMAX for Data Transmission' and is currently pursuing research in FPGA-based design and implementation of DUC DDC based OFDM for data and image transmission. With a background in semiconductor and wireless FPGA streams, he has contributed to both national and international publications and serves as a reviewer for the Global Journal of Research in Engineering (GJRE).

Educational Journey

Jain University

Professor

Experience

0 - 0

Research

FPGA Physical Layer Implementation of Fixed WIMAX for Data Transmission

Article January 23, 2026

The telecommunication area in last decade has witnessed the interest towards the providing the quality of service to the users but achieving this QoS with increasing users as the most significant issue. As a result, various technologies have come into existence. The broadband wireless access is one of the ways to reach the high business demand for increasing the internet connection. The wireless solution has been found to remove the limitations in capacity in comparison to wired technologies. The significant technique called OFDM (Orthogonal Frequency Division Multiplexing) provides the better QoS but leads to high Cyclic Prefix (CP). The implementation of WiMAX standards on FPGA is a big challenge as this wireless standard is a complicated standard. The hardware modeling made here to simulate the physical layer of WiMAX on FPGA evaluates the system performance. This paper introduces a design of WiMAX physical layer implemented over FPGA and analyzes the performance of the implemented system. The methodology here is first to design the hardware architecture of the system being implemented on the FPGA and then to transfer the design on the FPGA board. The system performance is evaluated by generating a random digital data and transferring the data from the transmitter on the implemented communication system. The received data is then compared with the transmitted data to evaluate the Bit Errorrate of the implemented system.