Abstract
This paper presents the systematic design approach of a low-power, medium- resolution, high-speed pipelined Analog-to- Digital Converter (ADC). Two Different Design Approach of 3 bit Structure , Frequency of 5 GHZ ,Supply Voltage 1.2 V with Slight Modification implemented in microwind software . By simulation their Power Dissipation Calculated , measured 50% less power Consumed in modified Pipelined ADC Design.
This paper presents the systematic design approach of a low-power, medium- resolution, high-speed pipelined Analog-to- Digital Converter (ADC). Two Different Design Approach of 3 bit Structure , Frequency of 5 GHZ ,Supply Voltage 1.2 V with Slight Modification implemented in microwind software . By simulation their Power Dissipation Calculated , measured 50% less power Consumed in modified Pipelined ADC Design.
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Ankur Modi. 1970. “. Global Journal of Research in Engineering – F: Electrical & Electronic GJRE-F Volume 11 (GJRE Volume 11 Issue F7): .
Crossref Journal DOI 10.17406/gjre
Print ISSN 0975-5861
e-ISSN 2249-4596
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