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Bench Marking Models of Low Power VLSI Testing Strategies: Current State of the Art
Y. Sreenivasula Goud, Dr.B.K.Madhavi
Volume 13 Issue 7
Global Journal of Research in Engineering
Volume 13 Issue 7
Global Journal of Research in Engineering
Testing time, power dissipation and others are major challenging optimization problems while testing digital circuits and VLSI circuits. Unluckily, most of these problems are frequently solved by heuristic ways which do not assure best solution. The analysis of situation of art models and answers in such optimization problems were carried out in this paper, especially for power optimization in digital VLSI circuit testing.
