Artificial Neural Networks (ANN) is significantly used in signal and image processing techniques for pattern recognition and template matching. Discrete Wavelet Transform (DWT) is combined with neural network to achieve higher compression if 2D data such as image. Image compression using neural network and DWT have shown superior results over classical techniques, with 70% higher compression and 20% improvement in Mean Square Error (MSE). Hardware complexity and powerissipation are the major challenges that have been addressed in this work for VLSI implementation. In this work, modified distributive arithmetic DWT and multiplexer based DWT architecture are designed to reduce the computation complexity of hybrid architecture for image compression. A 2D DWT architecture is designed with 1D DWT architecture and is implemented on FPGA that operates at 268 MHz consuming power less than 1W.