A circuit design for a new Low Power 4-bit Braun Multiplier is presented. The multiplier is implemented by using different Threshold Voltage techniques. Power reduction techniques are proposed for 4-bit Braun Multiplier which is designed by Full Adders. To get Optimum design low threshold voltages are used at critical paths similar way high threshold voltages are used at non critical paths. The design uses CMOS digital circuits in order to reduce the power dissipation while maintaining computational throughput. This architecture is simulated at 90nm Technology with 1.2v power supply. The power dissipation of nearly 46%, Power Delay Product of 56% and delay 19.3% has been reduced by using proposed techniques with good performance.