- Home
-
Board
- Editorial Board
- Apply For Reviewer
-
Research Publishing Standards
- Guidelines
- Peer Review Policy
- Short Guide to New Editors
- Retraction Guidelines
- Research Institute
- Recommendations for the Board of Directors
- Editor Research Audit and Service Assessments
- Guidelines for Journals Publishers
- Code of Conduct for Journal Publishers
- Commandment in Social Media
- Suggestions
- Authorship Disputes
- Rights and Responsibilities
- Editors Home
- Visibility
- Information
- Apply for Editorial
- About
- Call for Paper
- Research Community
-
Journals
- Computer Science
-
Medical Research
- A: Neurology & Nervous System
- B: Pharma, Drug Discovery, Toxicology & Medicine
- C: Microbiology & Pathology
- D: Radiology, Diagnostic Imaging and Instrumentation
- E: Gynecology & Obstetrics
- F: Diseasescancer, ophthalmology & pediatric
- G: Veterinary Science & Veterinary Medicine
- H: Orthopedic & Musculoskeletal System
- I: Surgeries & Cardiovascular System
- J: Dentistry & Otolaryngology
- K: Interdisciplinary
- L:Nutrition and Food Science
- Engineering
- Science Frontier Research
- Management
-
Human-Social Science
- A: Arts & Humanities psychology, public administration, library sciences, sports, arts, media, music
- B: Geography, Environmental Science & Disaster Management
- C: Sociology & Culture
- D: History, Archaeology & Anthropology
- E: Economics
- F: Political Science
- G: Linguistics & Education
- H: Interdisciplinary
-
Fellow
-
Support
Account
×
Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology
Md. Masood Ahmad, Dr. K.Manjunathachari, Dr. K.Lalkishore
Volume 16 Issue 1
Global Journal of Computer Science and Technology
Volume 16 Issue 1
Global Journal of Computer Science and Technology
In this paper a new full adder is proposed. The number of Transistors used in the proposed full adder is 13.Average leakage is 62% of conventional 28 transistor CMOS full adder. The leakage power reduction results in overall power reduction. The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tools.
